2002 – Present                Intel Corporation                           Santa Clara, CA

Principal Engineer

·       Researcher, manager at Intel Labs. Some of the work/products are confidential. Projects include:

·       Enabling mainstream parallel software development: Designed, architected, and prototyped nested data parallel and deterministic task parallel programming API called Ct. Comprised of compiler (prototype was static, current version is dynamic), runtime (memory management, threading, and language runtime components) and application libraries. Built team from 1 person to ~20 people divided between the U.S. and China. Heavily engaged with internal stakeholders and external partners from throughput computing and gaming market segments (Americas, Asia, Europe) to tailor design for real world usage. Taking prototype-level proof-of-concept to alpha/beta quality release within 12 months (from complete coding restart) with multiple architecture/ISA backends.

·       Many-core architectures: Characterization, simulation, and design of first many-core product. Enabled true multithreading suport in simulated workloads and build infrastructure for true cycle-accurate parallel application characterization.

·       Managed runtime environments, such as Java and .Net.

·       Memory hierarchy design and performance issues for multi-core architectures, compression in memory system design.

2001 – 2002                   Consultant                              Mountain View, CA

Consultant

·       Technical diligence work for investors in several areas including consumer electronics, memory design, and video compression.  References available upon request.

1998 - 2001                    Intensys Corporation                          San Jose, CA

Vice-President of Engineering & Chief Technical Officer

·       Full product lifecycle management for applications, tools, systems, and chips. From 1998 through 1999, managed entire software development effort, including both development tools and imaging/video applications.  In early 2000, assumed responsibility for entire engineering effort, including system board and chip development. Managed all aspects of product development cycle from market requirements docs through product requirements docs, specification and architecting, project resource planning and scheduling, vendor engagement (when appropriate), development, test, release, and support through select beta trials.

·       Under my guidance the engineering organization successfully designed and took to fabrication, tested, and demonstrated a prototype chip implementing Intensys’s proprietary architecture, built embedded development board, developed libraries for imaging devices (video, digital cameras, and printers), and developed an integrated development environment for developing software. Prototype system was rolled out at a major trade show and resulted in a pre-tapeout purchase order for both our chip and software from a major Taiwanese OEM.

·       Built a team of engineers with a range of backgrounds, including hardware/software managers, digital imaging/video scientists, compiler engineers, GUI developers, embedded systems engineers, and ASIC engineers.

·       Deep involvement in application efforts of core parallel computing technology to MPEG-4 coding, JPEG2000 coding, and protocol processing for transport offload engines in host-bus adapters. Efforts yielded architected solutions, market understanding, patents, and white papers.

·       Conceived of and designed signal processing-specific C language extensions, compiler architecture and optimizations, and development tool suite. Built team to develop the products.

·       Extensive presentation experience in customer and investor engagements. Intensys raised nearly $13 million in venture investment and yielded both a purchase order from a major Taiwanese OEM and an LOI from a major Japanese OEM. Extensive travel to meet and present to customers and potential investors in both the U.S. and Asia.

1997 - 1999                    MetaXen, LLC (Acquired by Exelixis) South SF, CA

Group Leader, Computational Sciences

·       Led development of MetaVision, a state-of-the-art toolset for mining databases of molecules for prospective drug candidates. Responsible for entire product development lifecycle, including product requirements, specification, architecting, project planning and budgeting, and staffing.

·       Principal involved in customer and investor pitches.

·       Created new state-of-the-art technologies for fast in silico screening of databases of molecular structures. Developed new learning-based pattern recognition techniques for parallel optimization of lead compounds for potency, specificity, and oral bioavailability properties.

1996 - 1997                    Stanford University                            Stanford, CA

Research Associate

·       Post-doctoral researcher in the SUIF (Stanford University Intermediate Format) compiler group in the Computer Science Department.

·       Worked under the direction of Monica Lam.

·       Led development team in developing SUIF Explorer, an interactive performance optimization environment integrating compiler analysis, performance profiling, and visualization techniques.

1989 - 1996                    Carnegie Mellon University              Pittsburgh, PA

Ph.D., M.S., Computer Science

·       Dissertation: Compiling Recurrent and Irregular Serial Code for High Performance Computers

·       Thesis Advisor: Allan L. Fisher, Ph.D.

1985 - 1989                    University of California                 Los Angeles, CA

B.S., Computer Science and Engineering

·       GPA > 3.8

·       Summa Cum Laude, Phi Beta Kappa

2000                             MIT Sloan, Stanford GSB

Executive Education Programs

Selected publications:

Anwar Ghuloum, Terry Smith, Gansha Wu, Xin Zhou, Jesse Fang, Peng Guo, Byoungro So, Mohan Rajagopalan, Yongjian Chen, Biao Chen. “Future Proof Data Parallel Algorithms and Software on Intel Multi-core Architecture”, Intel Technology Journal. http://www.intel.com/technology/itj/2007/v11i4/8-dataparallel/1-abstract.htm ( December 2007).

Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Mohan Rajagopalan, Richard L. Hudson, Leaf Petersen, Vijay Menon, Brian R. Murphy, Tatiana Shpeisman, Eric Sprangle, Anwar Rohillah, Doug Carmean, Jesse Fang: Enabling scalability and performance in a large scale CMP environment. EuroSys 2007: 73-86

Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Shobhit O. Kanaujia: Compression in cache design. ICS 2007: 190-201

Anwar Ghuloum, Eric Sprangle, Jesse Fang. “Flexible Parallel Programming for Tera-scale Architectures with Ct.” Intel Whitepaper, 2007.

Matthew Hammer, Umut Acar, Mohan Rajagopalan, and Anwar Ghuloum. “A Proposal for Parallel Self-Adjusting Computation”. In The Proceedings of the ACM SIGPLAN Workshop on Declarative Aspects of Multicore Programming, Nice, France 2006.

Allan L. Fisher and Anwar M. Ghuloum. "Parallelizing Complex Scans and Reductions." In the Proceedings of the ACM SIGPLAN '94 Conference on Programming Language Design and Implementation (PLDI), Orlando, FL, June 1994, pp. 135-146.

Anwar M. Ghuloum and Allan L. Fisher. "Flattening and Parallelizing Irregular, Recurrent Loop Nests." In Proceedings of Fifth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), Santa Barbara, CA, July 1995, pp. 58-67.

A. Ghuloum, C. R. Sage, and A. N. Jain. “Molecular Hashkeys: A Novel Method for Molecular Characterization and its Application to Predicting Important Pharmaceutical Properties of Molecules.” Journal of Medicinal Chemistry 42: 1739-1748, 1999.

S.W. Liao, A. Diwan, R. P. Bosch, A. Ghuloum, and M.S. Lam. “Suif Explorer: An Interactive and Interprocedural Parallelizer.” In Proceedings of the 7th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP), Atlanta, Georgia, May 1999.

F. Tam, R. Meier, D. Greenfield, X. Ouyang, and A. Ghuloum. “An MPEG-4 Solution on the Intensys Architecture.” White paper, Intensys Corporation, 2001.

R. Duncan and A. Ghuloum. “Mapping C-Extensions For Image Processing To Parallel Architectures”, Submitted for publication 2001.

Selected Patents:

9 pending patents.

Issued Patents:

#7143238 “A Method to Compress Data In Cache”

#7257693 “Multi-processor System That Employs A Compressed Cache Lines’ Worth of Information and Processor Capable of Use in Said System”

#7162584 “A Mechanism to Include Hints Within Compressed Data”

#7162583 “A Mechanism to Store Reordered Data with Compression”

#7243191 “Compressing Data in Cache Memory”